What is pulse divider?

Figure 1 is a D-type flip-flops of ÷ 2 crossover circuit. Pulse divider has a wide working frequency, low frequency-in fact there is no limit, limit frequency main high-end decided to use the device, but also has something to do with the circuit. 1 MHz to the following may use metal-oxide-semiconductor (MOS) integrated circuit, 1 ~ 30 MHz may use the Transistor-transistor logic (TTL) circuit, 30 ~ 60 MHz is the use of high-speed TTL circuits, 60 ~ 300 MHz should adopt emitter coupled logic (ECL) circuit. The N-class ÷ 2 divider in a series, may constitute ÷ 2N non-synchronous frequency divider. This level push level frequency chain have save device and limit the advantages of working frequency is high, but has the disadvantage of delayed accumulation, when the series N is large, the last stage rollover moments and first level compared with great delay, sequential circuits is not allowed. In addition, the crossover frequency is limited to 2N also inflexible. Figure 1 D-type flip-flops of ÷ 2 crossover circuit adopts stage feedback can implement any number of frequency division, as in Figure 2. Diagram of three triggers the same pulse sequences driven, when in need to Flip-Flip, belong to synchronize with a 600 MHz prescalers. It does not delay the accumulation of problems, and non-synchronous divider compared to obtain the same number of fractional frequency shall be more devices, and operating frequency is low. In addition there is also a pulse divider, their number can be used by external frequency signal reset, called program divider. This crossover circuit has been widely used in frequency synthesizer. Figure 2-level room feedback frequency