Digital signal processor features

Digital signal processors such as Intel, Pentium, or Power PC's general purpose processor (GPPs) are very different, these differences arise from the structure of DSPs and instruction is tailored to the signal processing design and development, it has the following features added hardware multiplication ·. (MACs) to effectively accomplish such as signal filtering, multiply-accumulate operation processor required for effective multiplication operation. GPPs initially was not as heavy design of the multiply operation, the DSPs with early GPPs distinguishes the first major technological improvements is added to a single cycle multiply operation of specialized hardware and clear MAC instruction. · Harvard structure traditional GPPs use Feng. Norman storage structure, in this structure, there is a storage space through two buses (an address bus and a data bus) connects to the processor core, which do not meet MAC must one instruction cycle storage for fourth visit to door requirements. General structure using Harvard DSPs, Harvard architecture, there are two storage space: the program storage space and data storage space. Processor core through two sets of bus connected with the storage space, allowing for storage at two access, this arrangement enables processor bandwidth doubled. In the Harvard architecture, sometimes through an increase in the second data storage space and bus to achieve greater storage bandwidth. Modern high-performance GPPs typically have two die angustifolia super high-speed buffer memory, a storage of data in a storage instructions. From theory, this dual-chip cache and bus connections equivalent to Harvard architecture, however, GPPs use control logic to determine which data and instructions Word resides in the on-chip cache, this procedure is not commonly seen for program designers, DSPs, program designers to explicit control over which data and instructions are stored in the chip storage unit or cache. · zero consumption cycle control DSP algorithm characteristics in common: most of the processing time is spent executing in relatively small circulation within a small number of instructions. Therefore, most of the DSP processors have zero consumption cycle control of specialized hardware. Zero consumption cycle refers to the processor to spend time testing cycle counter is unable to perform a set of instructions to complete the loop, hardware cycle jump and attenuation of the loop counter. Some DSPs had also adopted a directive of the cache to achieve high-speed single instruction cycle. · special addressing modes DSPs frequently contain a special address generator, which produces a signal processing algorithms require special addressing, such as cycle addressed and bit flipping addressing. Circular addressed correspond to flow FIR filtering algorithm, bit flipping addressing corresponds to the FFT algorithm. · execution time of predictability in the application of most of the DSP has hard real-time requirements in each case all work must be completed within a specified period of time. This real-time constraints require program designers identify each sample how much time or in the worst cases at least spent much time. The process of implementing procedures for DSPs for programmers is transparent, so it's easy to predict treatment each task execution time. However, for high-performance GPPs, due to the large number of ultra high speed data and procedures for the use of the cache, the dynamic allocation procedures, the execution time of forecasting becomes more complex and difficult. · rich peripheral DSPs have DMA, serial, parallel, timer, etc. Link peripherals.