The structure of a digital signal processor

Digital signal processor for higher performance because you cannot derive from the traditional structure of the solution, and therefore proposed a variety of strategies to improve performance. Which seems to be increasing clock frequency is limited, the best method is to improve the parallelism. Improve the operation of parallelism can be implemented by two ways: to enhance every instruction execution of operations, or enhance each instruction cycle execution of instructions. Both have had several requests in parallel DSPs new structure. Enhanced DSP processor DSP previously, using a complex, mix of instruction set that allows programming to take more action codes in one instruction. Traditional DSP processor in one instruction cycle only emits and executes one instruction. This single stream, complex instruction method allows to obtain very powerful DSP processor performance without requiring large amounts of memory. While maintaining the structure and the DSP instruction set unchanged, to increase the workload of each instruction, one approach is to use extra execution units and increase the data path. For example, some high-end DSP has two multipliers, instead of one. We use the DSP is called remote Luang gnawing Commission 9 Yan die cherry ðµðºð because their structure and the previous generation of DSP, but performance after the increase in the unit of execution has significantly increased. Of course, instruction set must also enhanced, such programming would be in a directive specifies more concurrent operations to take advantage of additional hardware. Enhanced DSPs examples are the DSP16000 Lucent, ADI's ADSP2116x. The advantage of enhanced DSPs is good compatibility, and DSP with earlier have similar costs and power consumption. The disadvantage is that complex structures, and the further development of the complex, the directive is limited. VLIW architecture as mentioned earlier, the traditional DSP processor uses a complex mixture of directives, and in one instruction cycle only flow out and executes one instruction. However, recently, some more DSP a RISC-based instruction set, and in one instruction cycle execution instructions can make use of the unified register file. For example, the Carmel, Siemems Philips TriMedia and TI's of TMS320C62XX processor family uses a VLIW (VLIW) structure. C62xx processors each time a 256-bit instruction package, and Pack resolves to eight 32-bit command, and then put them into its eight independent execution units. At best, C62xx simultaneous execution of eight directives dates this case reached a very high rate of MIPS (such as 1600MIPS). VLIW architecture advantage is high-performance, structured (potential easy programming and better target build system). The disadvantage is the high power consumption, code bloat-need wide program memory, new programming/compilation difficulties (tracking command arrangements, easily damaged pipeline down performance). Superscalar architecture like a VLIW Processor, superscalar architecture in parallel flow out and execute multiple commands. But with VLIW Processor, superscalar architecture does not clearly specify the need for parallel processing instructions, and instead use dynamic directive programming, according to the resources available to the processor, data dependencies and other factors to determine which commands to be executed simultaneously. Superscalar architecture have long used for high-performance general-purpose processors, such as a Pentium or PowerPC. Recently, the company developed the ZSP first commercial superscalar architecture DSP ZSP164xx. Superscalar has the advantage that there is a big leap in performance, well-defined, code width no significant growth. The disadvantage is that very high power consumption, dynamic arrangements directive code optimization problems. SIMD architecture single instruction multiple data (SIMD) processor to enter long data decomposition into several shorter data, and then by the single directive in parallel, thereby improving the handling of large volumes, the ability to decompose data. This technology can significantly enhance the multimedia and signal processing large-scale use of some vector operation speed of calculation, such as coordinate transformations and rotations. General-purpose processor SIMD enhanced two examples is the Pentium MMX and AltiVec extensions of the PowerPC family. Simd in some high-performance DSP processor also has application. For example, the DSP16000 in their data in a limited way support SIMD style of operation, and Analog Devices has recently launched a new generation of SHARC DSP processors, the capacity expansion. SIMD SIMD architecture as the bus, full data access resources, and does not need to change the signal processing (including images, voice) algorithm's basic structure, therefore more and more widespread use of SIMD architecture. SIMD architecture are experiencing issues with algorithms, data structures, must meet the requirements of the data processed in parallel, in order to accelerate the cycle often need to be opened and processed data needs to be rescheduled. Usually the fixed-point arithmetic SIMD support only. DSP/microcontroller mixed structure many applications need to control-oriented software and DSP software mixing. An obvious example is a digital cellular phone, for consisting of monitor and voice processing. In General, microprocessor control can provide good performance in the DSP performance was bad, dedicated DSP processor features just the opposite. Therefore, most recently some microprocessor manufacturers begin to offer DSP-enhanced version of the microprocessor. With a single processor to complete two software's mission is very attractive because it can potentially provide a simplified design and save layout space, reduce the total power consumption, lower system costs, etc. DSP and MCU combination methods are: · in a knot on the integration of a variety of processors, such as MotorolaDSP5665x · DSP as a co-processor, such as move ARMPiccolo · DSP core values to an existing bit processors such as SH-DSP · microcontroller and DSP have been integrated, as all TMS320C27xx · new design, such as the ability for DSP TriCore with demand, DSP processor architecture is a new and innovative design, DSP,MCU, CPU structure benefits mutual loan.