What is a digital signal processor speed standard?

Digital signal processor meets the design requirements, the key lies in the speed requirements are met. Test the speed of the processor has many methods, the most basic is the measurement of processor instruction cycle, that is, the fastest processor execution instruction time. Instruction cycle countdown divided by 1 million and then multiplied by each cycle number of instructions executed, the result is that the processor's highest rate, expressed in millions of instructions per second and MIPS. But the instruction execution time does not indicate the processor's true performance, different processors in a single command to accomplish the same amount, simply compare the instruction execution time and not just areas don't performance differences. Now some new DSP adopting VLIW (VLIW) schema, the schema, a single cycle time can implement more instruction, and each directive implements tasks less than traditional DSP, so relative VLIW and general DSP device, compare the size of the MIPS is misleading. Even in the comparison between traditional DSP MIPS size also has certain one-sidedness. For example, some processors allow in a single directive for several ongoing displacement, and some DSP a directive must be on a single data bit displacement; some DSP can and is doing ALU instructions-independent data for parallel processing (in the implementation of the directive while loading operands), but also some DSP can only support and ongoing ALU instructions for parallel processing of data; in some the new DSP allows in a single directive defines two MAC. Therefore only for MIPS and cannot be accurately obtained performance. Solving the above problems is to use a basic operation (instead of the directive) as a standard to compare performance. It is common to the MAC, the MAC operating time cannot provide more DSP performance differences of sufficient information, in the vast majority of DSP, MAC action only in a single instruction cycle, its Mac time equal to instruction cycle time, as noted above, some DSP in a single MAC cycle to process more than other DSP. MAC time and does not reflect such as cycle operation, performance, and such actions in all the applications are used. The most common approach is to define a set of routines that compare different DSP execution speed. This routine may be an algorithm of "core" features, such as FIR or IIR filters, etc., or the whole or part of the application (such as voice encoder). Figure 1 to use BDTI's tool to test the performance of several DSP devices. In comparing the DSP processor speed when its advertised MOPS (million operations per second) and MFLOPS (million floating point operations per second) parameter, because the different manufacturers on the understanding of the "actions", index of significance. For example, some processors can simultaneously floating-point multiplication operation and floating-point addition operation, thus advertised their products for MIPS MFLOPS. Secondly, in comparing the processor clock speed, DSP input clock rate as possible directive or directive rate twice to four times, different processors may not be the same. In addition, many DSP with a clock frequency multiplier or phase-locked loop, you can use external low-frequency clock on the high-frequency clock signal.