What is a digital signal processor memory management?

Digital signal processor (DSP) of the memory management performance by its DSP on storage subsystems of management ability. As mentioned earlier, MAC and other signal processing functions is DSP basic signal processing capabilities, fast MAC implementation capacity requirements in each instruction cycle from memory read an instruction word and two data word. There are several ways to implement this interface to read, including multiple storage (allowed in each instruction cycle storage multiple access), separation of instructions and data storage ("Harvard" structure and its derived classes), as well as the instruction cache (to allow from the cache read instruction instead of memory, storage is free up used for data reading). Figure 2 and Figure 3 shows the Harvard storage structure and many microcontrollers "Feng · Norman" structural differences. In addition to the support of the size of the memory space. Many fixed point DSP's main target market is an embedded application system, in which the application memory generally smaller, so this DSP devices with small to medium-on-chip memory (4K to 64K words or so), equipped with narrow external data bus. In addition, the vast majority of fixed-point DSP address bus is less than or equal to 16-bit, so you can add storage space is limited. Some floating-point DSP on-chip memory is very small, or no, but the external data bus width. For example, TI company 6K TMS320C30 only, on-chip memory to 24-bit external bus, 13-bit external address bus. While ADI's ADSP2-21060 has 4 MB on-chip memory that can divide a variety of ways to program memory and data storage. Select DSP, depending on the size of storage space, as well as on the request to the external bus.